The invention relates to a nonvolatile memory system allowing data to electrically be written or erased.
An erasable and programmable read only memory (EP-ROM) system, known to those skilled in the art, employs a floating gate type FET (field effect transistor) or an MNOS (metal nitride oxide semiconductor) type FET for its memory cell. It is also known that in a memory system using memory cells of the floating gate type, there are two known erasing methods to erase the contents of the memory cells; one for illuminating the contents of memory cells by ultraviolet rays and the other for electrically erasing the contents of the memory cells. The ultraviolet erasing method is advantageous in that a smaller number of transistors constituting memory cells are needed, but is disadvantageous in that a longer time is taken for erasing the memory contents. In this respect, it is desirable to employ the electrical erasing method.
A conventional electrically alterable nonvolatile memory system employing the electrical erasing method will briefly be described with reference to FIG. 1. As shown, unit memory cells Iao, Ia1, . . . and Ibo, Ib1, . . . are arranged in columns of a matrix array while unit memory cells Iao, Ibo, . . . , and Ia1, Ib1, . . . are arranged in rows. Each memory cell, for example, Iao, is comprised of a series circuit including an MOS-FET 2 and a floating gate type FET 3. For writing data into the memory cell, a voltage applied to the control gate of the floating type FET 3 must be opposite in polarity to that of a voltage applied to the same for erasing data stored in the memory cell. To this end, the control gate FET 3 must electrically be insulated from the substrate in a memory system design. In the circuit construction shown, the control gate of FET 3 can not be used when the memory system is decoded. To avoid this, the FET 2 is connected in series to the FET 3. In the memory cell selection, the memory cell Iao in this example is selected by driving a column line 4a to which a MOS FET 5a is connected in series; and by driving a row line 6ao connected to the gate of the MOS FET 2. The control gate of the floating gate type FET 3 is connected to a control line 6b.
FIG. 2 shows a cross sectional view of a unit memory cell. As mentioned above, the ultraviolet ray erasing method needs only one transistor for the unit memory cell while the electrical erasing method needs a couple of transistors 2 and 3, as shown in FIGS. 1 and 2.
Accordingly, an object of the invention is to provide an electrically alterable nonvolatile memory system of a type in which the contents of memory cells are electrically erasable and each memory cell is comprised of a single transistor.